What is “ATX 3.x” and the Difference Between ATX 3.0 and ATX 3.1(Last edited 5/14/2026) People often think that what makes a PSU “ATX 3.x ready” means that the PSU comes with a 12VHPWR or 12V-2x6 cable. But this cable is part of PCI-SIG’s PCIe 5 specification. The ATX specification is maintained by Intel. Although Intel referenced the PCIe cable in ATX 3.x, PCIe’s new connector existed first by a few months and its use remains optional under ATX 3.x. In this section I’ll focus strictly on the ATX 3.x requirements sans the cable; the PCIe 5 cable is covered later. Compared to earlier ATX revisions, an ATX 3.x power supply must explicitly tolerate short, high-magnitude power spikes. To meet this, the spec mandates larger energy storage, time-aware over-current protection, a beefed-up 12V rail design, and faster control loops. Both ATX 3.0 and 3.1 define a “power budget” requiring the PSU to sustain, for example, 200% of its continuous output for 100 µs and 180% for 1ms (and so on) without faulting. The below table comes from the ATX 3.0 documents.
In a traditional PSU, a sudden load increase causes voltage to sag, the feedback loop detects the droop, and the PWM controller raises its duty cycle or frequency to recover voltage. But that reaction can be too slow for modern GPU power excursions. To address this, ATX 3.x units may add a feed-forward path that watches current surges as well as voltage dips. Beyond extra control loops, an ATX 3.x design might include a larger bulk capacitor, more secondary capacitors, or an OCP scheme with time-based blanking that only trips if an over-current persists past both a magnitude and a duration threshold. Contrary to some press reports, ATX 3.0 did not introduce Alternative Low Power Mode (ALPM) hardware support to power supplies. That appeared in earlier ATX12V specifications. What changed in ATX 3.0 is that certain ALPM states became mandatory for the 5 VSB rail rather than merely “recommended.” Moving from ATX 3.0 (early 2022) to ATX 3.1 (late 2023), most updates are relaxations to make compliance easier. Full-load holdup time at 100% load dropped from 17ms to 12ms (the 17ms figure now only applies above 80% load), and the regulation window widened from ± 5% down to -7%, allowing for a 11.16V on the +12V rail. Finally, ATX 3.1 adds a formal definition for power excursions at the motherboard’s PCIe slot—recognizing that slot devices can impose the same abrupt demands as dedicated power connectors. The PCIe 5.0 12VHPWR ConnectorMid-2020 saw the PCI-SIG unveil a new single-connector solution capable of delivering 600W to PCIe card edges. They dubbed this connector "12VHPWR" (pronounced "Twelve Volt High Power") and distinguished it with an "H+" marking. According to the specifications, each pin within the 12-pin configuration must handle at least 9.2A. However, it's worth noting that terminal current ratings decrease as terminal density increases. For example, a terminal independently rated for 9.2A might only support 8.5A when configured in a 2x6 arrangement. The original 12VHPWR connector came with or without sideband terminals. The original specification for the Sense0 and Sense1 in the sideband, which was never utilized, can be found below.
Beyond Sense0 and Sense1, the standard defines two additional terminals that I haven't yet encountered implementation of in any actual power supplies. The first, CARD_PWR_STABLE, functions similarly to the PWR_OK signal on a standard 24-pin connector. It’s essentially a way for the GPU to communicate to the PSU that power delivery is functioning normally. The second terminal, CARD_CBL_PRES#, serves as an optional notification system that alerts the PSU when graphics cards are connected, allowing power-aware supplies to allocate their resources accordingly. By the time we started to see 12VHPWR connectors in the wild, this is what the definition of the sideband ended up being:
Clearly, if we have a 150W card, we don’t even need a sideband unless our card supports the CARD_PWR_STABLE and CARD_CBL_PRES# signals! I did check and, as I write this, I could find no 150W cards that utilized a 12VHPWR connector. The PCIe 5.1 12V-2x6 ConnectorThe 12VHPWR connector proved problematic from the start. Users discovered that the male and female connectors sometimes failed to fully engage, leading to dangerous overheating and melting at the connection point. This safety issue demanded a solution that wouldn't render existing hardware obsolete. PCI-SIG addressed this in early 2023 with their 5.1 specification revision, modifying only the PCB-side connector while leaving the cable connector unchanged, allowing for seamless backwards compatibility. The revised design recessed the terminals deeper into the housing by 0.1mm, requiring additional force for proper connection. Without complete engagement of the sense pins, the GPU now automatically refuses to initialize as a safety measure. Before: After: The updated specification maintains the requirement for each terminal to handle at least 9.2A, but now acknowledges real-world variability: "Inconsistent cable contact resistance may cause individual pins to carry currents exceeding 9.2A, though the complete assembly must still limit total current to 55A RMS per direction." Beyond the connector redesign, 150W graphics cards now implement a different sense pin configuration—instead of leaving both pins disconnected, the new standard requires the two sense pins to be electrically connected to each other.
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